Ottawa, Canada, March 01, 2007 -- Zarlink Semiconductor Inc. (NYSE/TSX:ZL) today expanded its family of Synchronous Ethernet timing solutions, with a new single-chip Gigabit Ethernet line card synchronizer that allows service providers to seamlessly and economically deliver time-critical applications over packet-based networks.

Available now, the ZL30107 chip provides timing and synchronization for Ethernet line cards in next-generation networking equipment supporting circuit services over IP-based architectures. Integrating independent analog and digital PLLs, the device synchronizes with standard telecom and Ethernet clocks and generates an IEEE 802.3 jitter compliant 25 MHz Gigabit Ethernet output clock. Backed by Zarlink's leading timing and synchronization expertise, no competing device can match the performance and level of integration at the price point supported by the ZL30107 device.

"Synchronous Ethernet is a key technology as service providers aggressively seek new ways to more efficiently support time-sensitive applications over packet networks," said Darren Ladouceur, marketing manager, Timing and Synchronization, Zarlink Semiconductor. "Building on our established synchronous Ethernet timing solutions, the ZL30107 chip allows manufacturers to easily build timing capabilities into next-generation networking equipment."

Currently, service providers must operate a number of different networks and deploy costly external mechanisms to support legacy services over IP architectures. For example, network synchronization between remote MSAPs (multi-service access platforms) are connected to central office equipment via T1/E1 or SONET/SDH links.

In comparison, synchronous Ethernet technology allows service providers to deliver all services over a single converged, high-bandwidth, synchronous Ethernet link.

The ZL30107 device supports synchronous, holdover and asynchronous free-run modes of operation. In synchronous operation, the ZL30107 PLL replaces the free-running reference clock usually provided by an oscillator with a network timing reference. The device accepts three references and performs hitless reference switching. The integrated DPLL automatically synchronizes to one of a pre-defined set of standard telecom frequencies ranging from 2 kHz to 77.76 MHz in addition to 25 MHz. The chip generates a very low jitter 25 MHz Gigabit Ethernet output clock.

When all references fail the device automatically enters holdover mode and continues to generate an output clock based on frequency data collected from past reference signals.

The chip defaults to asynchronous free-run mode, where the DPLL generates an output clock with frequency accuracy equal to an external oscillator or low-cost crystal. This allows equipment manufacturers to "build-in" synchronous Ethernet capabilities in next-generation networking equipment. Services providers can then easily enable synchronous Ethernet capability when it is required.

Synchronous Ethernet application note

Zarlink and Marvell recently demonstrated synchronization over the Ethernet physical layer using their respective PLL and Ethernet PHY technologies. An application note outlining Zarlink-Marvell interoperability is available online at: http://assets.zarlink.com/AN/ZLAN_211_AppNote_Jan07.pdf.

Availability

The ZL30107 chip is in volume production and offered in a 9 mm x 9 mm, 64-pin CABGA package. For more, visit http://products.zarlink.com/product_profiles/ZL30107.

Complete information on Zarlink's synchronous Ethernet timing technology, including detailed application notes and data sheets, is available to qualified customers. To learn how to become a qualified customer please send an email to Timingandsync@zarlink.com. Alternatively, contact your local sales representative.

About Zarlink Semiconductor

For over 30 years, Zarlink Semiconductor has delivered semiconductor solutions that drive the capabilities of voice, enterprise, broadband and wireless communications. The Company's success is built on its technology strengths including voice and data networks, optoelectronics and ultra low-power communications. For more information, visit http://www.zarlink.com/.

Shareholders and other individuals wishing to receive, free of charge, copies of the reports filed with the U.S. Securities and Exchange Commission and Regulatory Authorities, should visit the Company's web site at http://www.zarlink.com/ or contact Investor Relations.

Certain statements in this press release constitute forward-looking statements within the meaning of the Private Securities Litigation Reform Act of 1995. Such forward-looking statements involve known and unknown risks, uncertainties, and other factors which may cause the actual results, performance or achievements of the Company to be materially different from any future results, performance, or achievements expressed or implied by such forward-looking statements. Such risks, uncertainties and assumptions include, among others, the following: rapid technological developments and changes; our ability to continue to operate profitably and generate positive cash flows in the future; our dependence on our foundry suppliers and third-party subcontractors; order cancellations and deferrals by our customers; increasing price and product competition; and other factors referenced in our Annual Report on Form 20-F. Investors are encouraged to consider the risks detailed in this filing.

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Zarlink and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc.

For further information:

Edward Goffin
Media Relations
613 270-7112
mailto:edward.goffin@zarlink.com

Mike McGinn
Investor Relations
613 270-7210
mike.mcginn@zarlink.com