While the "all-IP" world will eventually be a reality, for an extended period of time synchronization will need to support a hybrid of both the older circuit-switched and the newer packet-based timing interconnections. This article discusses the transition of timing and line card synchronization to support hybrid circuit and packet networks, focusing on the board and chassis level and demonstrating how synchronization may be received from the network and how clocks can be routed internally to the system

Ensuring that routers, gateways or DSLAMs meet stringent timing specifications usually requires a specialized jitter/wander generator. In this Design Idea, Zarlink applications engineer Slobodan Milijevic describes how to use a standard function generator to more cost-effectively and efficiently measure jitter and wander tolerance.

In a typical telecommunication product, all cards are synchronized to the same clock. The failure of this clock disrupts the data traffic on all cards. To avoid this problem and increase network reliability, telecom products are designed with active and redundant clocks. In this article, Zarlink's Slobodan Milijevic outlines the importance of clock redundancy, presents two methods (parallel and serial) used to implement timing redundancy, and discusses the advantages and disadvantages of both approaches.